The present invention relates to a semiconductor memory device, more particularly, to a semiconductor memory device ensuring the resetting of bit lines even when a chip selection control signal represents a short period of a chip nonselection state.
In general, in a semiconductor memory device, the time for readout of data from the memory cells is shortened by resetting, during chip nonselection, the bit line pairs connected to the memory cells to an equal potential. Other than the bit line pairs, a semiconductor memory device has other complimentary signal line pairs such as data bus or output line pairs of a sense amplifier. Such complementary signal line pairs are also reset during chip nonselection. In these cases, it is required that the reset of the potential of the bit line pairs or the other complementary signal line pairs be performed reliably no matter how short the period of the chip nonselection state represented by a chip selection control signal.
In the past, it has not been possible to sufficiently reset the potential of bit line pairs or the other complementary signal line pairs when the period of the chip nonselection state is short. In this case, the problem occurs of a long being necessary for reading out data from the memory cells.